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ism band fsk receiver ic adf7902 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features single-chip, low power uhf receiver companion receiver to adf7901 transmitter frequency range: 369.5 mhz to 395.9 mhz eight rf channels selectable with three digital inputs modulation parameters supported fsk demodulation 2 kbps data rate 34.8 khz frequency deviation 5.0 v supply voltage low power consumption 18.5 ma with receiver enabled 1 a standby current 24-lead tssop general description the adf7902 is a low power uhf receiver. the device demodu- lates frequency shift keyed (fsk) signals with 34.8 khz frequency deviation and at data rates of up to 2 kbps. there are eight specific rf channels ranging from 369.5 mhz to 395.9 mhz on which the receiver can operate. each channel is selectable by configuring three digital control lines. the adf7902 is designed for low power applications, consuming 18.5 ma (typical) during normal operation and 1 a (maximum) in standby mode. functional block diagram if filter fsk demodulator cp lna vco pfd osc n divider select cpout vcoin osc1 clkout ch1_sel ch2_sel ch3_sel rx_data lna_1 lna_2 bias ldo1 ldo2 creg1 lna_rset rset gnd ce adf7902 clkout_enb vbat1 creg2 vbat2 osc2 cvco 06456-001 figure 1.
adf7902 rev. 0 | page 2 of 12 table of contents features .............................................................................................. 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 absolute maximum ratings............................................................ 4 esd caution.................................................................................. 4 pin configuration and function descriptions............................. 5 typical performance characteristics ..............................................6 applications information .................................................................7 applications circuits ....................................................................7 test modes..........................................................................................9 outline dimensions ....................................................................... 10 ordering guide .......................................................................... 10 revision history 1/07revision 0: initial version
adf7902 rev. 0 | page 3 of 12 specifications v dd =5.0 v; gnd = 0 v; t a = t min to t max , unless otherwise noted. typical specifications t a = 25c. table 1. parameter min typ max unit test conditions channel frequencies channel 1 369.5 mhz channel 2 371.1 mhz channel 3 375.3 mhz channel 4 376.9 mhz channel 5 388.3 mhz channel 6 391.5 mhz channel 7 394.3 mhz channel 8 395.9 mhz receiver parameters data rate 2 kbps frequency deviation ?34.8 khz data = 0 +34.8 khz data = 1 input sensitivity ?110 dbm lna input impedance 128 ? j125 ? f rf = 388.3 mhz channel filtering if filter bandwidth 200 khz ?3 db bandwidth adjacent channel rejection 60 db 1 mhz offset desired signal 3 db above input sensitivity level, with interferer power increased until ber = 10 ?3 phase-locked loop ce high to receive data 4 ms reference input crystal reference 9.8304 mhz 25 ppm frequency accuracy input logic levels input high voltage, v ih 0.7 v dd v input low voltage, v il 0.2 v dd v output logic levels output high voltage, v oh 4.5 v output low voltage, v ol 0.4 v output drive level 2 ma power supply voltage supply v dd 5 v current consumption receiver enabled 18.5 ma ce = 1 low power sleep mode 1 a ce = 0
adf7902 rev. 0 | page 4 of 12 absolute maximum ratings t a = 25c, unless otherwise noted. table 2. parameter rating vbat to gnd 1 ?0.3 v to +6.0 v digital i/o voltage to gnd ?0.3 v to vbat + 0.3 v lna_1, lna_2 0 dbm operating temperature range industrial (b version) ?40c to +85c storage temperature range ?40c to +125c maximum junction temperature 125c tssop ja thermal impedance 150.4c/w lead temperature, soldering vapor phase (60 sec) 235c infrared (15 sec) 240c 1 gnd = gnd1 = gnd1b = gnd2 = 0 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adf7902 rev. 0 | page 5 of 12 pin configuration and function descriptions rx_data creg2 test vbat2 ce gnd1 ch1_sel clkout ch2_sel ch3_sel clkout_enb cpout vcoin gnd2 cvco rset lna_rset lna_1 lna_2 creg1 vbat1 osc1 osc2 gnd1b adf7902 top view (not to scale) 1 2 3 4 5 24 6 7 8 9 10 11 12 23 22 21 20 19 18 17 16 15 14 13 06456-002 figure 2. pin configuration table 3. pin function descriptions pin no. mnemonic description 1 creg2 a 0.1 f capacitor should be added at creg2 to reduce regulator noise and improve stability. a reduced capacitor improves regulator power-on time but may cause higher spurs. 2 test test output pin. leave as no connect. 3 vbat2 5 v power supply for rf circuitry. decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. 4 ce chip enable input. driving ce low puts the part into power-down mode, drawing <1 a. 5 rx_data receiver output. demodulated data appears on this pin. 6 gnd1 ground for digital circuitry. 7 ch1_sel channel select pin. this repres ents the lsb of the channel select pins. 8 ch2_sel channel select pin. 9 clkout square wave clock output at the crystal frequency. this can be used to drive the osc2 pin of a partnering adf7902. the output has a 50:50 mark-space ratio and switc hes between 0 v and 2.2 v. if clkout is disabled by setting pin 11 high, then clkout must be tied low. 10 ch3_sel channel select pin. 11 clkout_enb clkout enable input. this should be driven low to enable the reference clock signal to appear on the clkout pin. driving the pin high removes the clock signal on clkout. it should be driven high when an external reference is used. 12 cpout charge pump output. this output genera tes current pulses that are integrated in the loop filter. the integrated current changes the control voltage on the input to the vco. 13 gnd1b ground for digital circuitry. 14 osc2 the reference crystal should be connected between this pin and osc1. the necessary crystal load capacitor should be tied between this pin and ground. a square wa ve signal can be applied to this pin as an external reference source. 15 osc1 the reference crystal should be connected between this pin and osc2. the necessary crystal load capacitor should be tied between this pin and ground. this pin shou ld be connected to ground when osc2 is driven by an external reference. 16 vbat1 5 v power supply for digital circuitry. decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. 17 creg1 a 0.1 f capacitor should be added at creg1 to reduce regulator noise and improve stability. a reduced capacitor improves regulator power-on time but may cause higher spurs. 18 lna_2 lna input. input matching is required between the antenna and the differential ln a input to ensure maximum power transfer. 19 lna_1 complementary lna input. 20 lna_rset external bias resistor for lna. a value of 1.1 k ? is recommended. 21 rset external resistor to set charge pump current and some internal bias currents. a value of 3.6 k ? is recommended. 22 cvco voltage controlled oscillator (vco) capacitor. a 22 nf capacitor should be placed between this pin and creg2 to reduce vco noise. 23 gnd2 ground for rf circuitry. 24 vcoin the tuning voltage on this pin deter mines the output frequency of the vco. the higher the tuning voltage, the higher the output frequency. the output of the loop filter is connected here.
adf7902 rev. 0 | page 6 of 12 typical performance characteristics 70 50 30 10 ?10 60 40 20 0 375.5 376.0 376.50 377.0 377.5 378.0 378.5 06456-003 rejection (db) frequency (mhz) carrier only interferer signal fsk interferer signal figure 3. narrow-band interference rejection plot 100 80 40 0 60 20 355 365 375 385 395 06456-004 rejection (db) frequency (mhz) carrier only interferer signal fsk interferer signal figure 4. wideband interference rejection plot 0 ?2 ?4 ?6 ?8 ?1 ?3 ?5 ?7 ?125 ?120 ?115 ?110 ?105 ?100 06456-005 log (ber) rf input level (dbm) ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 figure 5. sensitivity plot
adf7902 rev. 0 | page 7 of 12 applications information table 4. channel frequency truth table ch1_sel ch2_sel ch3_sel channel frequency (mhz) 0 0 0 369.5 1 0 0 371.1 0 0 1 375.3 1 1 0 376.9 0 1 0 388.3 1 0 1 391.5 0 1 1 394.3 1 1 1 395.9 applications circuits osc1 osc2 gnd2 vbat1 creg1 lna_2 lna_1 lna_rset vcoin rx_data ce vbat2 test creg2 gnd1 ch1_sel ch2_sel ch3_sel cpout clkout_enb clkout gnd2 cvco rset 5v 33pf 33pf 9.8304mhz 68nh 3.9pf 10pf 0.1f 62pf 1.1k ? 3.6k ? 22n f 680pf 15nf 150pf 820? 3.3k ? 0.1f 62pf 0.1f antenna matching crystal loop filter microcontroller 0.1f 06456-006 adf7902 5v 5v figure 6. single receiver applications circuit
adf7902 rev. 0 | page 8 of 12 osc1 osc2 gnd2 vbat1 creg1 lna_2 lna_1 lna_rset vcoin rx_data ce vbat2 test creg2 gnd1 ch1_sel ch2_sel ch3_sel cpout clkout_enb clkout gnd2 cvco rset 5v 68nh 3.9pf 10pf 0.1f 62pf 1.1k ? 3.6k ? 22nf 680pf 15nf 150pf 820 ? 3.3k ? 0.1f 62pf 0.1f matching 0.1f 0 6456-007 adf7902 (rx2) osc1 osc2 gnd2 vbat1 creg1 lna_2 lna_1 lna_rset vcoin rx_data ce vbat2 test creg2 gnd1 ch1_sel ch2_sel ch3_sel cpout clkout_enb clkout gnd2 cvco rset 5v 5v 33pf 33pf y1 crystal 62nh 3.9pf 6.8pf 0.1f 62pf 1.1k ? 3.6k ? 22n f 680pf 15nf 150pf 820 ? 3.3k ? 0.1f 62pf 0.1f matching 0.1f adf7902 (rx1) antenna microcontroller 5v 5v loop filter loop filter figure 7. dual receiver applications circuit
adf7902 rev. 0 | page 9 of 12 test modes if clkout_enb is tied high, clkout is disabled. the clkout pin is reconfigured as a test enable input. if the clkout pin is then tied low, the part operates as is normal with clkout off. if it is tied high (2.2 v), the part is in test mode. test mode is described in table 5 . when clkout_enb = 0, rssi appears on the test output pin (pin 2), and clkout is configured as an output with a 9.8 mhz clock coming out. when test mode is enabled, the channel frequency is set to 369.5 mhz (channel 1). table 5. test modes ch1_sel ch2_sel ch3_sel test mode 0 0 0 agc gain is set to maximum (filti is also set to maximum on test output pin) 0 0 1 filti on test output pin 0 1 0 filtq on test output pin 0 1 1 charge pump output is set to ma ximum (test pin is also tri-state) 1 0 0 charge pump output is set to minimum (a lso n-divider output 2 on test output pin) 1 0 1 charge pump is tri-state (test pin is also tri-state) 1 1 0 n-divider output 2 on test output pin 1 1 1 recovered data clock on test output pin
adf7902 rev. 0 | page 10 of 12 outline dimensions 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad figure 8. 24-lead thin shrink small outline package [tssop] (ru-24) dimensions shown in millimeters ordering guide model temperature range package description package option ADF7902BRUZ 1 ?40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 ADF7902BRUZ-rl 1 ?40c to +85c 24-lead thin shrink sma ll outline package [tssop], 13 reel ru-24 ADF7902BRUZ-rl7 1 ?40c to +85c 24-lead thin shrink sma ll outline package [tssop], 7 reel ru-24 1 z = pb-free part.
adf7902 rev. 0 | page 11 of 12 notes
adf7902 rev. 0 | page 12 of 12 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06456-0- 4/07(0)

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